In semiconductor equipment, the 12 layers PCB boards a crucial role in connecting core chips, transmitting high-frequency signals, and high currents. Its manufacturing process requires extremely high precision, stability, and reliability requirements. Compared to ordinary multi-layer printed circuit boards, 12 layers printed circuit boards have a more complex structure, more process steps, and need to adapt to the strict standards of semiconductor equipment for signal integrity and heat dissipation. Therefore, there are multiple core difficulties in the manufacturing process. Starting from the key process steps, we will break down the manufacturing challenges of 12 layers printed circuit boards in semiconductor equipment application scenarios.
1, Laminated process: the challenge of "precise bonding" in multi-layer structures
Layering is the core process of 12 layers PCB manufacturing, which requires the integration of 12 layerss of substrate, copper foil, and insulation layer into a whole through high temperature and high voltage. The difficulty lies in the alignment accuracy and thickness uniformity between layers, which are crucial for signal transmission in semiconductor equipment.
From the perspective of inter layer alignment, a 12 layers PCB needs to be pressed multiple times, and each pressing must ensure that the alignment error of each layer's graphics is controlled within a very small range. However, in actual manufacturing, the substrate is prone to thermal deformation at high temperatures, and there may be slight deviations in the flatness of the sheet after each lamination. When stacked on 12 layerss, the total alignment error may exceed the critical value. Once the alignment accuracy does not meet the standard, the transmission loss of high-frequency signals in semiconductor equipment will significantly increase, and even signal crosstalk may occur, affecting the normal operation of the equipment.
Uniformity of thickness is equally challenging. The 12 layers PCB needs to control the overall thickness and the deviation range of each layer thickness. However, during the compression process, uneven pressure distribution and differences in shrinkage rates between the substrate and insulation layer can lead to problems such as "thick in the middle, thin at the edges" or local protrusions in the final board. For areas in semiconductor equipment that require the installation of precision connectors, excessive thickness deviation can lead to poor connector contact and increase the risk of equipment failure.
2, Micro hole processing: dual challenges of small pore size and aspect ratio
The 12 layers PCB of semiconductor equipment requires a large number of micropores to achieve interlayer circuit connections. These micropores are not only small in size, but also need to penetrate 12 layerss of substrate, with a depth to diameter ratio far exceeding that of ordinary multi-layer printed circuit boards, greatly increasing the manufacturing difficulty.
Firstly, there is the issue of drilling accuracy. Due to the extremely small aperture, the drill bit is prone to "vibration" during high-speed rotation, resulting in aperture deviation and even scratches on the hole wall. At the same time, the material differences of the 12 layers substrate will accelerate the wear rate of the drill bit. If not replaced in time, the pore size accuracy of the subsequent micropores will continue to decrease. For semiconductor devices, the deviation of micro pore size can lead to uneven thickness of the copper layer inside the plated holes, intensify local heating during current transmission, and affect the heat dissipation performance of the device.
The deeper challenge lies in the quality of the pore wall. The micropores of a 12 layers PCB need to go through a "drilling de drilling electroplating" process, in which the de drilling process requires the removal of residual resin debris from the hole wall. However, the narrow pore size of the micropores makes it difficult for the cleaning solution to fully penetrate. If the de drilling is not thorough, the copper layer cannot tightly bond with the hole wall during electroplating, and "hole wall peeling" may occur during later use, causing circuit breakage. In addition, excessive aspect ratio makes it difficult for the current to be evenly distributed to the bottom of the hole during electroplating, and the thickness of the copper layer at the bottom of the hole is insufficient. In high current scenarios of semiconductor devices, the copper layer at the bottom of the hole is prone to overheating and burning out.
3, Copper thickness control: the contradiction between global uniformity and local thickening
The requirement for copper thickness in the 12 layers PCB of semiconductor equipment has a "duality": on the one hand, the global copper thickness needs to be uniform to ensure stable signal transmission; On the other hand, some areas require local thickening of copper thickness to enhance heat dissipation and current carrying capacity, which can easily lead to conflicts in manufacturing.
The difficulty in achieving global copper thickness uniformity lies in the electroplating process. The area of a 12 layers PCB is usually large, and the current distribution in the plating tank is easily affected by the shape of the board and the position of the hanging fixture, resulting in differences in copper thickness between the edges and the center of the board. In addition, the micro holes and blind holes in the 12 layers PCB will 'divert' current, causing the surface copper thickness near the holes to be thinner than other areas. If the global copper thickness deviation is too large, the signal transmission speed of different paths in semiconductor equipment will differ, resulting in data synchronization delay and affecting equipment processing efficiency.
Local thickening of copper thickness poses a risk of "excessive electroplating". To achieve local thickening of copper thickness, secondary electroplating needs to be carried out in the corresponding area. However, during secondary electroplating, the current is prone to diffuse to the surrounding areas, causing the copper thickness in non target areas to exceed the standard. At the same time, the transition between the locally thickened area and the surrounding conventional copper thick area is prone to "steps". During the subsequent coating of the solder mask layer, bubbles or insufficient thickness are easily generated at the steps, resulting in the exposure of the copper layer and increasing the risk of oxidation and short circuit in semiconductor equipment.
4, Solder mask coating: a balance between thin coating and high insulation
The solder mask layer of the 12 layers PCB in semiconductor equipment needs to meet both the requirements of "thin coating" and "high insulation" to adapt to the compact installation space and high-voltage working environment inside the equipment. However, there is a natural contradiction between these two requirements in manufacturing.
The coating accuracy of thin coatings is difficult to control. The solder mask layer is usually processed by screen printing or spray coating, and for the subtle bumps and depressions on the surface of the 12 layers PCB, thin coatings are prone to "leakage" or "uneven thickness". For example, if the pressure control of the scraper is improper during screen printing, the thickness of the solder mask layer at the step may be lower than the standard value. However, a thin solder mask layer can lead to a decrease in insulation performance, and high-voltage signal transmission in semiconductor equipment is prone to breakdown, causing equipment failure.
High insulation imposes strict requirements on the material and curing process of solder resist. During the operation of semiconductor equipment, printed circuit boards are exposed to high temperatures for a long time and may come into contact with corrosive gases. Solder resist must have excellent resistance to high temperatures and corrosion. However, under thin coatings, the distribution of curing agents in solder resist is prone to unevenness, resulting in insufficient cross-linking density in some areas after curing, and cracking is prone to occur in high-temperature environments, leading to a rapid decline in insulation performance over time.
5, Flatness control: a key constraint for later assembly and heat dissipation
The 12 layers PCB of semiconductor equipment needs to have extremely high flatness, otherwise it will affect the adhesion with chips and heat sinks, leading to poor heat dissipation or assembly failure. However, the multi-layered structure and complex process of 12 layers printed circuit boards make flatness control a "stubborn problem" in manufacturing.
On the one hand, the stress release after multi-layer compression can cause the board to warp. During multiple lamination processes on a 12 layers PCB, the internal stress of each layer material accumulates continuously. After cooling, the stress is released, which can easily cause the board to bend towards the thicker side of the copper foil. Especially when there is a significant difference in local copper thickness, the warpage may far exceed the requirements of semiconductor equipment.
On the other hand, the high-temperature treatment of subsequent processes will exacerbate the issue of flatness. The processes such as solder mask curing need to be carried out at a certain high temperature. At this temperature, the PCB board will undergo thermal deformation again. If the stress is not fully released before, the deformation will further overlap. For areas in semiconductor devices that require close contact with heat sinks, flatness deviations can lead to reduced contact area, decreased heat dissipation efficiency, increased chip operating temperature, and shortened device lifespan.
6, Testing and Repair: Quality Control Challenges in Complex Structures
The manufacturing process of 12 layers PCB for semiconductor equipment requires 100% full inspection, but due to the complex structure, some defects are difficult to detect, and the difficulty of repair is extremely high, becoming a major difficulty in quality control.
In the inspection process, defects in the inner layer of the 12 layers PCB are difficult to detect through conventional appearance inspection and require X-ray detection and ultrasonic scanning. However, X-ray detection has limited recognition rate for small defects and cannot determine the bonding state between the hole wall and the inner copper foil; Although ultrasonic scanning can detect interlayer bonding, the scanning resolution may decrease due to the thickness of 12 layerss, which may miss local debonding areas. These undetected defects will gradually expand during long-term operation of semiconductor equipment, ultimately leading to circuit failures.
The challenge in the repair process is even greater. If a short circuit or poor micro hole plating is detected in the inner layer, the 12 layers PCB needs to be "repaired layer by layer", that is, the insulation layer and copper foil are peeled off layer by layer, the defects are repaired, and then re pressed. However, during the layering process, high temperatures and chemical reagents can easily damage the surrounding intact layers, resulting in a lower success rate of repairs. Even if the repair is successful, new stress concentrations may still occur in the re pressed area. In the vibration environment of semiconductor equipment, cracks are prone to occur at the repair site, becoming a new potential fault hazard.